PCB[edit]
PLD's[edit]
Lower PCB[edit]
| PLD Information | Credits | Download | View | ||||
|---|---|---|---|---|---|---|---|
| Dump Method | Target Device(s) | Location | Status | Creator(s) | Tester(s) | Files | Pictures |
| Bruteforced | GAL16V8 | 6J | Tested | Caius | Caius | JEDEC | |
| Bruteforced | GAL16V8 | 6K | Tested | Caius | Caius | JEDEC | |
Upper PCB[edit]
| PLD Information | Credits | Download | View | ||||
|---|---|---|---|---|---|---|---|
| Dump Method | Target Device(s) | Location | Status | Creator(s) | Tester(s) | Files | Pictures |
| Modified | GAL22V10 | A1 | Tested | Caius | Caius | JEDEC | |
For A1, tie pin 10 to 12 when install chip in socket. Original device was a PAL16L8 but unable to fit equations into device