(→PLD's) |
(→PLD's) |
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|[[File:R-Type bootleg PLDs.jpg|100px]] | |[[File:R-Type bootleg PLDs.jpg|100px]] | ||
|} | |} | ||
== Notes == | |||
<pre> | |||
The PAL16R8 (3) needed to be programmed to a GAL16V8-15 otherwise artifacts appear in sprites | |||
</pre> | |||
== Credits == | == Credits == | ||
*PCB & IC pictures from Caius | *PCB & IC pictures from Caius | ||
*PLD's provided by Caius | *PLD's provided by Caius | ||
Revision as of 08:58, 4 August 2021
PCB
-
Top board
-
Middle board
-
Bottom board
PLD's
| PLD Information | Credits | Download | View | ||||
|---|---|---|---|---|---|---|---|
| Dump Method | Target Device(s) | Location | Status | Creator(s) | Tester(s) | Files | Pictures |
| Unlocked
Converted |
PAL16R4
GAL16V8 |
1 | Tested | Caius | Caius | ZIP | 
|
| Unlocked
Converted |
PAL16R4
GAL16V8 |
2 | Tested | Caius | Caius | ZIP |
|
| Unlocked
Converted |
PAL16R4
GAL16V8 |
3 | Tested | Caius | Caius | ZIP |
|
Notes
The PAL16R8 (3) needed to be programmed to a GAL16V8-15 otherwise artifacts appear in sprites
Credits
- PCB & IC pictures from Caius
- PLD's provided by Caius