(→PLD) |
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== PLD == | == PLD == | ||
{ | {{PLD_ALL}} | ||
|- | |- | ||
|Bruteforced | |Bruteforced |
Revision as of 17:05, 30 June 2021
PCB
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CPU Board
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Video Board
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Sub Board (top)
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Sub Board (bottom)
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Sub Board (under PAL)
PLD
PLD Information | Credits | Download | View | |||||
---|---|---|---|---|---|---|---|---|
Dump Method | Target Device | Location | ID | Status | Creator(s) | Tester(s) | Files | Pictures |
Bruteforced | GAL16V8 | Sub PCB | Tested | Porchy | Porchy | JEDEC |
PROM to GAL
PLD Information | Credits | Download | ||||||
---|---|---|---|---|---|---|---|---|
Original Device | Target Device | Location | ID | Status | Notes | Creator(s) | Tester(s) | Files |
MMI 6301-1 (82S129) | GAL16V8 | IC101 | 21J-K-0 | Tested | Tie pin 8 to 10 | Caius | Caius, Porchy | JEDEC |
Reference
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Schematics
Credits
- PCB pictures by Porchy
- IC picture by Porchy