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== Schematic == | == Schematic == | ||
<gallery> | <gallery> | ||
[[File:Amstrad_CPC6128_Schematic.png | [[File:Amstrad_CPC6128_Schematic.png]] | ||
</gallery> | </gallery> | ||
Revision as of 12:50, 19 February 2021
PLD
| PLD Information | Credits | Download | View | |||||
|---|---|---|---|---|---|---|---|---|
| Dump Method | Target Device | Location | ID | Status | Creator(s) | Tester(s) | Files | Pictures |
| Recreated | GAL16V8 | IC118 | 40031 | Tested | Porchy, Arnoldemu | Porchy, Bryce | ZIP | |
Schematic
Notes
Manually recreated by Porchy using logic analyser. This chip makes heavy use of latches in order to implement memory bank switching.