(→PLD's) |
|||
| Line 27: | Line 27: | ||
|Unlocked | |Unlocked | ||
|[[GAL20V8]] | |[[GAL20V8]] | ||
|D21 | |[[SQUASH_D21|D21]] | ||
|Tested | |Tested | ||
|[[Caius]] | |[[Caius]] | ||
Revision as of 12:46, 15 January 2023
PCB
PLD's
| PLD Information | Credits | Download | View | ||||
|---|---|---|---|---|---|---|---|
| Dump Method | Target Device(s) | Location | Status | Creator(s) | Tester(s) | Files | Pictures |
| Unlocked | GAL16V8 | F2 | Tested | Caius | Caius | JEDEC | 
|
| Unlocked | GAL16V8 | J16 | Tested | Caius | Caius | JEDEC | 
|
| Unlocked | GAL20V8 | D21 | Tested | Caius | Caius | JEDEC | 
|
| Unlocked | GAL20V8 | H11 | Tested | Caius | Caius | JEDEC | 
|
Credits
- PCB and IC pictures from Caius