360 PLD-A1

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Found on...[edit]

Equations[edit]

INPUT FROM_3, FROM_21, FROM_8, RAM_OE, ADSP_BMS, D2, D1, NQ2, A0, A1, ADSP_IOMS, ADSP_SCLK1, ADSP_DMS, RAM_WR, ADSP_RESET, D0, RJ4, J4_68;
OUTPUT OE_374, TO_11, CLK1, TO_33, ROM_BANK_OE, DAC_CLK, TO_13, ROM_OE1, RAM_CE1, RAM_CE2, ADSP_WR, J4_41, J4_43, J4_73, J4_74;

OUTPUT A21 CLOCKED_BY FROM_21 RESET_BY /ADSP_RESET;
OUTPUT A22 CLOCKED_BY FROM_21 RESET_BY /ADSP_RESET;
OUTPUT A23 CLOCKED_BY FROM_21 RESET_BY /ADSP_RESET;

OUTPUT RAM_A13 CLOCKED_BY FROM_3 RESET_BY /ADSP_RESET;
OUTPUT RAM_A14 CLOCKED_BY FROM_3 RESET_BY /ADSP_RESET;

NODE L_RAM_CE  CLOCKED_BY FROM_3  RESET_BY /ADSP_RESET;
NODE L_ROM_OE1 CLOCKED_BY FROM_21 RESET_BY /ADSP_RESET;
NODE L_ADSP_WR CLOCKED_BY FROM_8  RESET_BY /ADSP_RESET;

ROM_BANK_OE = ADSP_BMS + RAM_OE + RJ4 + J4_68;

DAC_CLK = /ADSP_SCLK1;

OE_374 = RAM_OE + ADSP_IOMS + /A1 + /A0;
CLK1   = RAM_WR + ADSP_IOMS + /A1 + /A0;

TO_11  = RAM_WR + ADSP_IOMS +  A1 +  A0;
TO_13  = RAM_WR + ADSP_IOMS +  A1 + /A0;
TO_33  = RAM_WR + ADSP_IOMS + /A1 +  A0;

A21 = D0;
A22 = D1;
A23 = D2;

RAM_A13 = D0;
RAM_A14 = D1;

L_RAM_CE = D2;
RAM_CE1 = ADSP_DMS +  L_RAM_CE;
RAM_CE2 = ADSP_DMS + /L_RAM_CE;

L_ROM_OE1 = D2 + D1 + D0;
ROM_OE1 = ADSP_BMS + L_ROM_OE1;

J4_41 = ADSP_BMS +  J4_68 + RJ4;
J4_43 = J4_68 +  RJ4;
J4_73 = ADSP_BMS +  A21 +  L_ROM_OE1 + /A23;
J4_74 = ADSP_BMS + /A21 + /L_ROM_OE1 + A23;

L_ADSP_WR = D0;
ADSP_WR = NQ2 + L_ADSP_WR;