02-28-01

Found on...

• Ataxx

Equations

/*********************************************************/
/* U3 on Ataxx JAMMA adapter labeled 02-28-01            */
/* Makes CSYNC from VSYNC and HSYNC                      */
/* Shortens VSYNC from 16 HSYNC cycles to 2 HSYNC cycles */
/*********************************************************/

/** Inputs **/

pin 1   = HS_CLK; /* HSYNC clock input for registers */
pin 2   = VSYNC; /* VSYNC (VBLANK) input */
pin 7   = HSYNC; /* HSYNC logic input */
pin 11  = !OE; /* /OE input for registered outputs */

/** Outputs **/

pin 13  = CSYNC; /* CSYNC output */
pin 14  = CNT0; /* Bit 0 (LSb) of internal 4-bit counter */
pin 15  = CNT1; /* Bit 1 of internal 4-bit counter */
pin 16  = CNT2; /* Bit 2 of internal 4-bit counter */
pin 17  = CNT3; /* Bit 3 (MSb) of internal 4-bit counter */
pin 18  = VS_INT; /* Internal VSYNC signal */
pin 19  = CS_INT; /* Internal CSYNC signal */

/** Logic Equations **/

/* 4-bit counter, counts on rising edge of HSYNC, resets to 1111 when VSYNC is high */
CNT0.d = VSYNC # !CNT0;
CNT1.d = VSYNC # (CNT1 $ CNT0);
CNT2.d = VSYNC # (CNT2 $ (CNT1 & CNT0));
CNT3.d = VSYNC # (CNT3 $ (CNT2 & CNT1 & CNT0));

/* VS_INT is high for two HSYNC clock cycles after VSYNC falls */
VS_INT = !VSYNC & !CNT1 & !CNT2 & !CNT3;

/* CS_INT combines HSYNC and VS_INT */
CS_INT = HSYNC & !VS_INT;

/* CSYNC inverts CS_INT */
CSYNC = !CS_INT;