Difference between revisions of "Amstrad 6128"
From
Line 29: | Line 29: | ||
== Schematic == | == Schematic == | ||
<gallery> | <gallery> | ||
[[File: | [[File:Amstrad CPC6128 Schematic.png]] | ||
</gallery> | </gallery> | ||
Revision as of 12:51, 19 February 2021
PLD
PLD Information | Credits | Download | View | |||||
---|---|---|---|---|---|---|---|---|
Dump Method | Target Device | Location | ID | Status | Creator(s) | Tester(s) | Files | Pictures |
Recreated | GAL16V8 | IC118 | 40031 | Tested | Porchy, Arnoldemu | Porchy, Bryce | ZIP |
Schematic
Notes
Manually recreated by Porchy using logic analyser. This chip makes heavy use of latches in order to implement memory bank switching.