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Applied Engineering QuadraLink: Difference between revisions

From PLD Archive
Created page with "== PCB == <gallery> File:AppliedEngineeringQuadraLink.jpg </gallery> == PLD == {{PLD_ALL}} |- |Glitched |GAL16V8 |U1 |QL1A.I |Tested |Bolle |Bolle |[https://wiki.pldarchive.co.uk/pals/Applied_Engineering_Quadralink_U1.jed JED] | |- |Glitched |GAL16V8 |U2 |QL2A.I |Tested |Bolle |Bolle |[https://wiki.pldarchive.co.uk/pals/Applied_Engineering_Quadralink_U2.jed JED] | |} == Credits == *PCB picture from Bolle Category:Computer Ca..."
 
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|{{PLD|Applied_Engineering_Quadralink_U2.zip}}
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Revision as of 12:23, 7 December 2024

PCB


PLD

PLD Information Credits Download View
Dump Method Target Device Location ID Status Creator(s) Tester(s) Files Pictures
Glitched GAL16V8 U1 QL1A.I Tested Bolle Bolle Applied_Engineering_Quadralink_U1.zip
Glitched GAL16V8 U2 QL2A.I Tested Bolle Bolle ZIP

Credits